1. Field of the Invention
The invention is generally directed to physical vapor deposition (PVD) sputter systems. The invention is more specifically related to an apparatus and method for PVD sputtering during the fabrication of semiconductor devices wherein it is desirable to obtain a combination of uniform deposition thickness, high deposition rate, and good step coverage.
2. Cross Reference to Related Publications
The following publication(s) is/are believed to be related to the present application and is/are cited here for purposes of reference:
(A) D. S. Bang. et al, "Modeling of Ti Physical Vapor Deposition Systems", IEEE International Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits (NUPAD V, Honolulu) Jun. 1994, pp 41-44; PA1 (B) D. S. Bang. et al, "Profile Modeling of Collimated Ti Physical Vapor Deposition", 10th Symposium on Plasma Processing, Electro Chemical Society, San Francisco, May 1994; and PA1 (C) G. Box and N. Draper, "Empirical Model Building and Response Surfaces", John Wiley & Son, New York 1987.
3. Description of the Related Art
PVD sputtering is used within semiconductor processing and other arts for depositing metal films and the like onto substrate surfaces.
The substrate (e.g., semiconductor wafer) is typically a planar disk that is positioned, face-down at the top of a vacuum plasma chamber.
A planar target is further typically positioned face-up within the chamber, in spaced apart and symmetrical counterfacing relation with the substrate. In older sputter systems the target was on top and the substrate on the bottom. The substrate-on-top versus on-bottom orientation has to do with keeping the substrate surface clean and is not directly related to the present invention. For purposes of consistency, the older configuration with the substrate on the bottom will be shown, but it is to be understood that other orientations are fully within the contemplation of this disclosure.
The target is made of the material that is to be sputter deposited onto the substrate surface. Examples include, but are not limited to, metals such as aluminum (Al), titanium (Ti), copper (Cu), and alloys or compounds of these materials.
Emission-inducing energy is applied to the active face of the target in the form, for example, of a plasma containing accelerated argon ions. In response to such bombardment, the active face of the target emits small particles composed of the target material (e.g. aluminum). The emitted particles follow a generally linear trajectory from their point of emission on the target surface to a collision point on the counterfacing surface of the substrate. Physical adhesion mechanisms cause the target particles to bond to the surface of the substrate.
The physical dimensions and positionings of the substrate and target play important roles in determining rate of deposition and the uniformity of the deposited film. The distribution of emission-inducing energy across the target also plays a role.
Ideally, the target should be very wide relative to the substrate so that the target represents an infinite source plane to the particle-receiving face of the substrate. In a such a situation, if the particle receiving face of the substrate is perfectly planar and parallel to the target, every point on the substrate receiving face will receive the same contribution of deposition particles and film thickness will be uniform across the entire substrate.
Unfortunately, this ideal arrangement is not possible in practical implementations of PVD sputter chambers. The target has a finite size that is usually the same order of magnitude as that of the substrate. Non-uniformities develop across the substrate for characteristics such as deposition film thickness and deposition rate due to boundary conditions.
In the fabrication of semiconductor devices, the substrate surface is often not perfectly planar. Nonlinear features such as channels and mesas are typically found on the semiconductor substrate. It is often desirable to coat the sidewalls and/or bottoms of each channel or mesa with a layer of deposition material having a prescribed thickness. However, the linear nature of the trajectories followed by the emitted target particles in PVD systems create shadow effects. Not every portion of the substrate surface receives the same amount of target material at the same rate in the case where the substrate surface includes nonlinearities such as channels or mesas.
The term, "channel" is used herein in a broad sense to include features in semiconductor devices and the like such as contact vias, trenches, and other depressions which are to be fully or partially filled with deposition material.
The term, "mesa" is similarly used herein in a broad sense to include any device feature rising above a surrounding plane where the feature and/or its surrounding plane are to be coated with deposition material.
The term, "step coverage" is used herein in a qualitative sense to refer to the ability to coat one or more sidewalls or bottom of a channel or mesa to a desired thickness. The term, "step coverage" is further used herein in a quantitative sense to refer to the ratio of film thickness at the bottom of a sidewall relative to film thickness at the top of the same sidewall, where the sidewall has a predefined height.
The term, "step coverage uniformity" is used herein in a quantitative sense to mean the statistical standard deviation (sigma) of step coverage across a given substrate.
The term, "flat coverage uniformity" is used herein in a quantitative sense to mean the statistical standard deviation (sigma) of film thickness across a given substrate taking into consideration only substantially planar regions (not step regions) of the substrate surface.
The term, "film thickness uniformity" is used herein in a quantitative sense to mean the statistical standard deviation (sigma) of film thickness across a given substrate, taking into consideration all regions (flat and step regions) of the substrate surface.
The term, "bottom coverage uniformity" is used herein in a quantitative sense to mean the statistical standard deviation (sigma) of film thickness across a given substrate, taking into consideration only regions at the bottom of channels or mesas.
It has been common practice in the semiconductor fabrication arts to sputter deposit films to a thickness substantially greater than the desired or minimally acceptable amount in order to make sure that adequate thickness is obtained across the entire substrate despite nonuniformities in step coverage and film thickness. Sometimes, the extra-thick portions of the deposited material have to be polished away or otherwise removed in order to obtain planarity and/or uniform flat coverage across the substrate. Such over-deposition followed by removal of excess material is wasteful of resources, time, and energy.
It has also been common practice in the semiconductor fabrication arts to increase the radius of wafers every so many years in order to obtain higher yield per wafer and/or in order to be able to economically mass produce integrated circuit chips of larger dimensions. Alterations in wafer size have previously required major alterations to production equipment, including making physical vapor deposition sputter chambers of larger size to house larger and larger targets. PVD sputter chambers typically need to support ion plasmas at very low pressures, on the order of 2 milliTorr or less, and are thus relatively costly to manufacture. It would be desirable to have a PVD sputter system that can accommodate wafers of different sizes while providing relatively similar uniformities in step coverage and film thickness.